Position:  Postdoctoral Researcher

Current Institution:  University of Texas at Austin

Abstract:  Towards Smarter Hardware Prediction Mechanisms

In today’s data-driven world, memory system performance remains critical to the overall performance of many workloads. My research focuses on improving memory system performance by building smarter hardware prediction mechanisms. In particular, I have developed novel caching and prefetching solutions that improve significantly over prior art by exploring larger design spaces. For example, for cache replacement where previous solutions use heuristics targeting specific access patterns, I proposed Hawkeye, a cache-replacement policy which accommodates all access patterns by learning from Belady’s optimal solution (ISCA 2016). Similarly, for irregular data prefetchers where existing solutions are limited to a few access patterns, I proposed the Irregular Stream Buffer (ISB), which realizes the previously unattainable combination of two popular learning techniques — namely, address correlation and PC-localization (MICRO 2013). Finally, when considering the interaction between cache replacement and prefetching, I uncovered a new design space that is bounded by Belady’s 52-year-old prefetch-agnostic optimal solution on one end and our new prefetch-aware optimal solution on the other end (ISCA 2018). This new design space led to the development of the Harmony cache replacement policy which won the Cache Replacement Championship in 2017. Looking to the future, I believe that many other system optimizations — including both hardware and software optimizations — will benefit from a systematic exploration of larger design spaces.  But as systems get more complex, it will be difficult to navigate these design spaces with human insight alone. Therefore, one important goal of my future research is to leverage sophisticated machine learning algorithms to help system designers build highly accurate memory optimizations.

Bio:
Akanksha Jain is a postdoctoral researcher at the University of Texas at Austin. She received her PhD in computer science from The University of Texas in December 2016. She received bachelor’s and master’s degrees in computer science and engineering from the Indian Institute of Technology Madras in 2009. Her research interests are in computer architecture with a particular focus on the memory system and on using machine learning techniques to improve the design of memory system optimizations. Her work has been recognized with a best paper honorable mention at MICRO 2013, a Micro Top Picks honorable mention in 2016, and the first-place award at the Cache Replacement Championship in 2017.