Position:  PhD Student

Current Institution:  Stanford University

Abstract: 2D Materials for CMOS and Memory Integration

Modern CPU performance is reaching a plateau due to the scaling limitations of transistor technology. Additionally, a “memory wall” between CPU and memory has become a significant limitation as data usage has expanded exponentially requiring future computer technology to directly integrate memory and transistor devices. Layered two-dimensional (2D) materials have show promise for overcoming key CPU limitations due to their intrinsically thin body that is preferable for device scaling. Also, the weak layer boding allows for low-temperature transfer processing which is suitable for 3D monolithic CPU integration. I first studied the high-mobility 2D material black phosphorous (BP) transistors for Complementary Metal-Oxide-Semiconductor (CMOS) low-power digital circuits. It is required to develop both n- and p- type devices using the same semiconductor material to create CMOS technology. My work demonstrated that BP can be used as an effective n-type transistor by using ultra-low work function metals, achieving record high n-type current. I discovered the physical mechanisms of controlling doping and de-pinning effects for n- and p-type BP transistors, pushing BP closer to CMOS implementations. I have also focused on the integration of memory and transistors for memory arrays with a complete 2D material system using hexagonal-Boron Nitride (hBN) as a memory cell and monolayer Molybdenum Disulfide (MoS2) as the transistor selector. Utilizing the transferrable feature of 2D material, I demonstrated the very low processing temperature for a transistor switching memory structure and achieved the first two floor stacking of transistor switching memory cell in a monolithic 3D structure. Besides using MoS2 transistor as a selector, I also investigated using nonlinear electrical transport in 2D material out-of-plane direction for two terminal selectors which can greatly reduce the unit cell area. This 2D system can be easily integrated for monolithic 3D CPUs, overcoming the “memory wall”.

Bio:
Ching-Hua (Fiona) Wang is a PhD student in the Electrical Engineering Department at Stanford University, supervised by Professor H.-S. Philip Wong.  She received a Master’s degree in electronic engineering from the National Tsing-Hua University in 2009, then participated in the 20 nm CMOS front-end R&D group at TSMC for two years.  She also worked on nonvolatile memory in the Ya-Chin King and Chrong-Jung Lin research group, published at IEDM (2010 and 2013), and won the Taiwanese Government Scholarship for PhD programs. Her PhD research has focused on the development of 2D material applications for transistors and memory. She received a best-in-session award at SRC Techcon 2017 for her work on Scandium contacts to black phosphorus. She is currently working on hetero-structure 2D materials for memory application, including 2D transistor switching 2D RRAM and a 2D material based selector for 3D monolithic process.